The present invention relates to a structure of an integrated circuit device.
FIG. 8 is a schematic plan view showing a conventional general semiconductor integrated circuit. As seen from FIG. 8, a group of cells 2A, . . . 2B each having a prescribed circuit function are arranged on the main surface of a single semiconductor chip 1A, and wiring is made between predetermined cells of the group to constitute an entire circuit. Bonding pads 5 arranged on the semiconductor chip 1A serve to connect electrodes within the chip to external wirings.
Because of the above structure of the conventional semiconductor integrated circuit device, as in the case where an I/O pin 3a of the cell 2A is connected to an I/O pin 3b of the cell 2B on the semiconductor chip 1A, the distance between the cells is disadvantageously lengthened with an increase in the number of cells in the group and advancement scale of the integration. This leads to an increase in the chip area and delay of signals. In the future, these problems will become more remarkable with an increase in the integration scale.